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-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:03:11 03/25/2011 
-- Design Name: 
-- Module Name:    Mult2_1DATA - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.Definitions.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Mult_Data_Port is
    Port ( dataw 		: in  data_word_type;
           portw 		: in  port_word_type;
           is_load 	: in  STD_LOGIC;
			  output 	: out  std_logic_vector (7 downto 0));
			  
end entity Mult_Data_Port;

architecture Behavioral of Mult_Data_Port is

begin

process(dataw, portw, is_load) is
begin
	case is_load is
		when '1' => 
			output <= dataw;
		when others =>
			output <= portw;
	end case;

end process;

end Behavioral;

